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// Copyright 2019 Google
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdint.h>
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#include "Crashlytics/Crashlytics/Helpers/FIRCLSFeatures.h"
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#if CLS_CPU_X86_64
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enum {
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CLS_DWARF_X86_64_RAX = 0,
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CLS_DWARF_X86_64_RDX = 1,
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CLS_DWARF_X86_64_RCX = 2,
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CLS_DWARF_X86_64_RBX = 3,
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CLS_DWARF_X86_64_RSI = 4,
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CLS_DWARF_X86_64_RDI = 5,
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CLS_DWARF_X86_64_RBP = 6,
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CLS_DWARF_X86_64_RSP = 7,
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CLS_DWARF_X86_64_R8 = 8,
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CLS_DWARF_X86_64_R9 = 9,
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CLS_DWARF_X86_64_R10 = 10,
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CLS_DWARF_X86_64_R11 = 11,
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CLS_DWARF_X86_64_R12 = 12,
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CLS_DWARF_X86_64_R13 = 13,
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CLS_DWARF_X86_64_R14 = 14,
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CLS_DWARF_X86_64_R15 = 15,
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CLS_DWARF_X86_64_RET_ADDR = 16
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};
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#define CLS_DWARF_REG_RETURN CLS_DWARF_X86_64_RET_ADDR
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#define CLS_DWARF_REG_SP CLS_DWARF_X86_64_RSP
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#define CLS_DWARF_REG_FP CLS_DWARF_X86_64_RBP
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#define CLS_DWARF_MAX_REGISTER_NUM (CLS_DWARF_X86_64_RET_ADDR)
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#elif CLS_CPU_I386
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enum {
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CLS_DWARF_X86_EAX = 0,
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CLS_DWARF_X86_ECX = 1,
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CLS_DWARF_X86_EDX = 2,
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CLS_DWARF_X86_EBX = 3,
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CLS_DWARF_X86_EBP = 4,
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CLS_DWARF_X86_ESP = 5,
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CLS_DWARF_X86_ESI = 6,
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CLS_DWARF_X86_EDI = 7,
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CLS_DWARF_X86_RET_ADDR = 8
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};
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#define CLS_DWARF_REG_RETURN CLS_DWARF_X86_RET_ADDR
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#define CLS_DWARF_REG_SP CLS_DWARF_X86_ESP
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#define CLS_DWARF_REG_FP CLS_DWARF_X86_EBP
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#define CLS_DWARF_MAX_REGISTER_NUM (CLS_DWARF_X86_RET_ADDR)
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#elif CLS_CPU_ARM64
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// 64-bit ARM64 registers
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enum {
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CLS_DWARF_ARM64_X0 = 0,
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CLS_DWARF_ARM64_X1 = 1,
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CLS_DWARF_ARM64_X2 = 2,
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CLS_DWARF_ARM64_X3 = 3,
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CLS_DWARF_ARM64_X4 = 4,
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CLS_DWARF_ARM64_X5 = 5,
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CLS_DWARF_ARM64_X6 = 6,
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CLS_DWARF_ARM64_X7 = 7,
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CLS_DWARF_ARM64_X8 = 8,
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CLS_DWARF_ARM64_X9 = 9,
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CLS_DWARF_ARM64_X10 = 10,
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CLS_DWARF_ARM64_X11 = 11,
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CLS_DWARF_ARM64_X12 = 12,
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CLS_DWARF_ARM64_X13 = 13,
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CLS_DWARF_ARM64_X14 = 14,
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CLS_DWARF_ARM64_X15 = 15,
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CLS_DWARF_ARM64_X16 = 16,
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CLS_DWARF_ARM64_X17 = 17,
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CLS_DWARF_ARM64_X18 = 18,
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CLS_DWARF_ARM64_X19 = 19,
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CLS_DWARF_ARM64_X20 = 20,
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CLS_DWARF_ARM64_X21 = 21,
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CLS_DWARF_ARM64_X22 = 22,
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CLS_DWARF_ARM64_X23 = 23,
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CLS_DWARF_ARM64_X24 = 24,
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CLS_DWARF_ARM64_X25 = 25,
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CLS_DWARF_ARM64_X26 = 26,
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CLS_DWARF_ARM64_X27 = 27,
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CLS_DWARF_ARM64_X28 = 28,
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CLS_DWARF_ARM64_X29 = 29,
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CLS_DWARF_ARM64_FP = 29,
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CLS_DWARF_ARM64_X30 = 30,
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CLS_DWARF_ARM64_LR = 30,
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CLS_DWARF_ARM64_X31 = 31,
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CLS_DWARF_ARM64_SP = 31,
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// reserved block
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CLS_DWARF_ARM64_D0 = 64,
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CLS_DWARF_ARM64_D1 = 65,
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CLS_DWARF_ARM64_D2 = 66,
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CLS_DWARF_ARM64_D3 = 67,
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CLS_DWARF_ARM64_D4 = 68,
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CLS_DWARF_ARM64_D5 = 69,
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CLS_DWARF_ARM64_D6 = 70,
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CLS_DWARF_ARM64_D7 = 71,
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CLS_DWARF_ARM64_D8 = 72,
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CLS_DWARF_ARM64_D9 = 73,
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CLS_DWARF_ARM64_D10 = 74,
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CLS_DWARF_ARM64_D11 = 75,
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CLS_DWARF_ARM64_D12 = 76,
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CLS_DWARF_ARM64_D13 = 77,
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CLS_DWARF_ARM64_D14 = 78,
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CLS_DWARF_ARM64_D15 = 79,
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CLS_DWARF_ARM64_D16 = 80,
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CLS_DWARF_ARM64_D17 = 81,
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CLS_DWARF_ARM64_D18 = 82,
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CLS_DWARF_ARM64_D19 = 83,
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CLS_DWARF_ARM64_D20 = 84,
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CLS_DWARF_ARM64_D21 = 85,
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CLS_DWARF_ARM64_D22 = 86,
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CLS_DWARF_ARM64_D23 = 87,
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CLS_DWARF_ARM64_D24 = 88,
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CLS_DWARF_ARM64_D25 = 89,
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CLS_DWARF_ARM64_D26 = 90,
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CLS_DWARF_ARM64_D27 = 91,
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CLS_DWARF_ARM64_D28 = 92,
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CLS_DWARF_ARM64_D29 = 93,
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CLS_DWARF_ARM64_D30 = 94,
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CLS_DWARF_ARM64_D31 = 95
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};
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#define CLS_DWARF_MAX_REGISTER_NUM (CLS_DWARF_ARM64_SP)
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#define CLS_DWARF_REG_RETURN CLS_DWARF_ARM64_LR
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#define CLS_DWARF_REG_SP CLS_DWARF_ARM64_SP
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#define CLS_DWARF_REG_FP CLS_DWARF_ARM64_FP
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#endif
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#define CLS_DWARF_INVALID_REGISTER_NUM (CLS_DWARF_MAX_REGISTER_NUM + 1)
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